Shared Memory Machines

Summary

• Shared Memory Model
  • Dance Hall Architecture
  • Symmetric Multi Processor
  • Distributed Shared Memory Architecture
• Shared Memory and Caches
  • Memory Consistency and Cache Coherence
  • Hardware Cache Coherence
• Scalability

Shared Memory Model

Dance Hall Architecture

Cache specified per CPU

All CPUs have access to all memory

Symmetric Multi Processor

All cpus have acces to the bus

Symmetric because access times are all the same

Distributed Shared Memory Architecture

CPUs still all have access to each others memory, but it’s faster to access the memory in your tree

Shared Memory and Caches

Using a system bus (like with the SMP), CPU can access cache and only wait ~2 cycles, but may take +100 cycles to get main memory.

• Then it has to put it in cache anyway

CPU access and cache works identically to single cpu systems except for shared mutable data

• Cache coherence problem

Memory Consistency and Cache Coherence

Memory Consistency answers the question, “What is the model presented to the programmer?”.

Cache coherence answers the question, “How is the system implementing the model in the presence of private caches?”.

Hardware Cache Coherence

Write Invalidate

• If a variable is written into one cache, invalidate it everywhere else

Write Update

• Write to all caches

Scalability

When you add processors, you can exploit parallelism, but you increase overhead

If you want good performance, don’t share memory across threads, as much as possible.

Shared memory machines scale well when you don’t share memory.

– Chuck Thacker